TSMC focuses on power and efficiency with the new 2nm node

The Taiwan Semiconductor Manufacturing Co. (TSMC) has just officially unveiled its 2nm node, called the N2. The new process, which will be released sometime in 2025, introduces a new production technology.

According to TSMC’s teaser, the 2nm process will either offer a pure performance improvement over its predecessor or, when used at the same power level, will be much more energy efficient.


TSMC spoke extensively about the new 2N technology and explained the inner workings of the architecture. The 2N will be TSMC’s first node to use gate all-round field effect transistors (GAAFETs) and will increase the chip density across the N3E node by 1.1 times. Before the 2N is ever released, TSMC will launch 3nm chips, which have also been teased at the TSMC Technology Symposium in 2022.

The 3nm node will come in five different levels and with each new release, the number of transistors will increase, increasing the chip’s performance and efficiency. Starting with the N3, TSMC will later release the N3E (Enhanced), N3P (Performance Enhanced), N3S (Density Enhanced) and finally the “Ultra-High Performance” N3X. The first 3nm chips are expected to hit the market in the second half of this year.

While the 3nm process is closer to us in terms of its launch date, the 2nm is a bit more interesting, even if it’s still a few years away. The goal of TSMC with the 2nm node seems clear: to increase the performance per watt to allow for higher output levels as well as efficiency. The architecture as a whole has much to recommend. Let’s take the GAA nanosheet transistors as an example. They have canals surrounded by gates on all sides. This will reduce leakage, but the channels can also be widened, providing a performance boost. Alternatively, the channels can be reduced in size to optimize power costs.

Both the N3 and N2 will offer significant performance gains over the current N5, and all offer the choice of balancing power consumption with performance per watt. As an example (shared for the first time by Tom’s Hardware), comparing the N3 to the N5 yields an up to 15% gain in raw performance and a power reduction of up to 30% when used on the same frequency. The N3E will take those numbers even further, to 18% and 34% respectively.


Now, the N2 is where it starts to get exciting. We can expect a performance improvement of up to 15% when operated with the same power consumption as the N3E node, and if the frequency is reduced to the levels provided by the N3E, the N2 will deliver up to 30% lower power consumption.

Where is the N2 used? It will likely make its way into chips of all kinds, ranging from mobile system-on-a-chips (SoCs), high-end graphics cards, and equally advanced processors. TSMC has said that one of the hallmarks of the 2nm process is “chiplet integration”. This means that many manufacturers can use the N2 to use multi-chiplet packages to pack even more power into their chips.

Smaller process nodes are never bad. Once there, the N2 will deliver high performance to all types of hardware, including the best CPUs and GPUs, while optimizing power consumption and thermals. But until that happens, we’ll have to wait. TSMC won’t start mass production until 2025, so realistically, 2nm-based devices are unlikely to hit the market before 2026.

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